FMAC-1 Project begins! FMAC is beginnign a CubeSat satellite design project to build a constellations of 1U birds for Space Weather research.  For more information.

FMAC is developing code for use in the MISSE project that will place Virtex-4 FPGA devices outside the International Space Station for analysis of effects of radiation on these devices. Graduate students from UNM are performing this research. For more information.

This project involved using an embedded processor on the ML-403 platform to take in image and video as inputs and provide output based on processed data on various algorithms.  The transfer of data to the FPGA, both still image and video, is performed over an RS-232 connection running at 19.2kbs.  The data can be processed on the FGPA using Sobel edge detection and convolution algorithms. Click here to download the project report.  Click here to download the entire project in a zipped form.  For more information.

The DLX processor is a based on the RISC architecture and is used primarily for educational purposes. This report describes our work on the DLX architecture for the spring 2007 semester. Included in this report are our problems that we have had throughout the semester and how we corrected these problems. Problems that have not yet been corrected are also included in this report. Our current goals are also included within this document.

The main purpose of this project was to efficiently implement a SIMD performance scheme for the DLX architecture. This goal was ultimately changed due to conflicting issues between simulation and synthesizable code. The new goal was changed to implement the DLX architecture on a Xilinx Virtex II Pro FPGA board. The specific board device we are using is the XC2VP30, FF896 Flip-Chip Fine-Pitch BGA package. Our project used the VHDL code provided by Peter J. Ashenden’s case study of the DLX computer system to run and test the DLX architecture. For more information.

The main objective of this project was to utilize simulation tools for modeling a communications system that is comprised of several subsystems. Not long ago, it could take quite some time to prototype a single industrial product whereas today a concept can be simulated and tested thus yielding meaningful data as to whether a design is feasible for further research and/or development in hardware.  This communications system was modeled in MATLAB’s Simulink with Xilinx’s System Generator for DSP. The communications system is comprised of encoder, scrambler, shaping filter, modulation with a carrier signal, and noise exhibited in the channel.  For more information.

As image processing techniques and algorithms continue to advance, there is a need for systems that run these algorithms to be reconfigurable.  This need makes the Field Programmable Gate Array (FPGA) an excellent platform for image processor system development. This project set out to implement image-processing algorithms utilizing the Xilinx Virtex-II Pro, specifically on the Xilinx University Program (XUP) Development System.  Images are pre-processed using Matlab to produce a gray scale matrix represented as ASCII characters, which is then stored in a .hex file.  The file will then be sent serially using the Windows Hyperterminal to the FPGA.  The FPGA stores the incoming data to on-chip memory using software that runs on the FPGA through the Microblaze soft microprocessor. The image enters the FPGA as a bit stream through the RS-232 UART, and then is stored in a FIFO single stacked 64k BRAM block.  At this point the bytes of memory can be processed with a Sobel Edge Detector filter or a Convolution filter.  The filters will be imported as peripherals through the Xilinx Platform Studio (XPS) and packaged as recognized IP-Cores so the Microblaze processor can access them.  The image will then be stored back in the BRAM block, into a receive buffer, and finally captured back into the PC through the Hyperterminal and stored in a .txt file. The output files can then be post-processed in Matlab to view the results as images. For more information.

The AFRL-UNM MPP (HERC) is a reconfigurable, multiprocessor, general-purpose high-end computer. Its design is mainly focused on modularity and scalability while providing a reconfigurable, microprocessor-based platform. It was also conceived to explore the tradeoffs involved in designing a multiprocessor system constrained by the fact that all the main processing blocks are embedded in FPGAs.

The main component of the system is the Basic Module (BM), shown in Figure 13. It is a completely functional computational unit, composed of a Xilinx Virtex-4 FX100 FPGA, two DDR2 memory modules, a USB 2 host interface, Ethernet, System ACE, Analog-to-Digital Converters (ADCs), and four network interfaces. A single BM can be used as the processing unit of a single-powered system or as the building block of a system with a medium or a high number of processing units. For more information.

 Victor Murray's research is oriented to image and video processing using and developing AM-FM algorithms. The goal is to use those algorithms in motion estimation of ultrasound videos, having the carotid artery as principal application. Also, the developing of state of the arts labs in digital systems together with the design of hardware using VHDL into FPGAs for specific application are his research interests.  For more information.

Reconfigurable architectures for signal processing

Reconfigurable logic is being widely used as a hardware platform for the realization of signal and image processing algorithms. This is mainly due to its inherent suitability to implement parallel structures and to provide performance comparable to hardware-based designs, while maintaining flexibility similar to software-based designs. Common DSP algorithms implementations, such as convolution, FFT, DCT and others have been repeatedly reported in the literature. We intent to demonstrate that FPGAs - through partial run-time reconfiguration - can also provide dynamic precision support such as to improve a algorithm's numerical stability. For practical purposes, any feasible architecture must minimize reconfiguration time overhead and reconfiguration frequency in order to be advantageous. New architectures for basic arithmetic operations are proposed, that will reduce both of these factors to allow practical implementation of most common DSP algorithms where a dynamic precision might be of use.

Additionally, a custom design flow is provided, for rapid prototyping of embedded systems incorporating the new architectures proposed.  For more information.

Motion estimation with applications to ultrasound videos

Using the velocity estimates and applying a Kalman filter the reconstruction of pixel trajectories is possible and further used to study motion patterns of different objects and regions within a video. Along with this research interests, further work is done developing class material on DSP applications using FPGAs and Xilinx design tools for the ECE 539 class. For more information.

XUP-UNM Prototype Platform

This project was undertaken  as a joint endeavor between the Albuquerque Xilinx facility, XUP,  and the EECE Department of the University of New Mexico. It was born  based on donations receive as part of the XUP V1000 program. The lead  engineer for the project from the University of New Mexico is Craig  Kief. The design team consists of Allison Tafoya, Joe Eddie Leyba, Leslie Vonderheide, and Alonzo Vera. They received technical guidance from Dr. Howard Pollard (EECE), Jason Moore (Phoenix Xilinx), and Frank Wirtz (Albuquerque Xilinx). The overall plan used XCV1000BG560 FPGA devices to build  a prototyping platform that would provide other educational institutions a capability to explore a multitude of possibilities in programmable logic at a relatively low cost.  For more information.

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